Slew-aware Fast Clock Tree Synthesis with Buffer Sizing

被引：0
|
作者：
Choi, Mujun [1 ]
Oh, Deokkeun [1 ]
Kim, Juho [1 ]
机构：
[1] Sogang Univ, Dept Comp Sci & Engn, Seoul, South Korea
来源：
2018 INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION, AND COMMUNICATION (ICEIC) | 2018年
关键词：
skew; slew; buffer sizing; DME; Fast CTS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Clock tree synthesis (CTS) is a critical part on the total performance of chip. Buffer insertion is required in clock tree to prevent signal degradation and satisfy slew constraints. Also, buffer sizing minimizes power and skew in clock tree network. In this paper, we proposed slew-aware fast buffer insertion/sizing methodology in CTS based on DME to meet the skew constraints. The experiment results show the proposed sizing method reduce about 13.47% power consumption and 49.03% runtime compared to LP-based method.
引用
收藏
页码：271 / 274
页数：4
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