VLSI Architectures for Soft-Decision Decoding of Reed-Solomon Codes

Soft-decision decoding of Reed-Solomon codes delivers significant coding gains over classical minimum distance decoding. In this paper, we present architectures for polynomial interpolation and factorization, the two main steps of the soft-decoding algorithm. We introduce an algorithmic transformation for reducing the iterations required in generating the interpolation polynomial and present efficient architectures by sharing computations. We also describe algorithmic transformations for further reducing the interpolation and factorization latency. An area efficient, folded-pipelined version of the interpolation architecture is also described. Finally, we present an example of a Reed-Solomon soft decoder utilizing the presented architectures, having a 250 Mbps throughput.