Digitally Intensive Wireless Transmitter Architecture Employing RF Pulse Width Modulation

A digitally-intensive Cartesian RF transmitter based on three-level pulse width modulation (PWM) is proposed. The architecture utilizes two PLL-based RF-PWM generators to modulate baseband I and Q signals to switching signals at RF, which are used to drive class-D output stages. Due to the use of a ring voltage controlled oscillator (VCO), the architecture is wellsuited for multiband operation. A switched capacitor technique is used to provide a differential three-level RF-PWM output. The proposed transmitter is simulated in a 65-nm CMOS process, and achieves a peak output power of 22 dBm with 48% and 33% peak power added efficiency (PAE) at 900 MHz and 1.95 GHz respectively.