Layout design of high-quality SOI varactor

This paper presents the geometry effect on the characteristics of accumulation type SOI varactor with Mesa-isolation technology. Constant gate area varactors with various geometry condition were implemented to investigate the effects of layout design parameters on overall varactor performance. Physical and mathematic analysis based on the measurement results show that parasitic capacitance at the edge of active region seriously degrads the device quality factor at smallest gate length. The optimized SOI varactor has a quality factor Q of about 150 /GHz/pF at medium gate length varactor. The experiment result can serve as a design reference for high-quality SOI varactors.