Layout design of high-quality SOI varactor

被引：1

作者：

Chen, HY ^{[1
]}

Chen, KM ^{[1
]}

Huang, GW ^{[1
]}

Huang, CH ^{[1
]}

Yang, TH ^{[1
]}

Chang, CY ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 30050, Taiwan

来源：

2003 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS | 2003年

关键词：

D O I：

10.1109/VTSA.2003.1252606

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents the geometry effect on the characteristics of accumulation type SOI varactor with Mesa-isolation technology. Constant gate area varactors with various geometry condition were implemented to investigate the effects of layout design parameters on overall varactor performance. Physical and mathematic analysis based on the measurement results show that parasitic capacitance at the edge of active region seriously degrads the device quality factor at smallest gate length. The optimized SOI varactor has a quality factor Q of about 150 /GHz/pF at medium gate length varactor. The experiment result can serve as a design reference for high-quality SOI varactors.

引用

页码：273 / 275

页数：3

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