Distributed arithmetic in the design of high speed hardware fuzzy inference systems

被引：0

作者：

Gaona, A ^{[1
]}

Olea, D ^{[1
]}

Melgarejo, M ^{[1
]}

机构：

[1] Univ Distrital Francisco Jose de Caldas, Lab Automat Microelect & Computat Intelligence, Bogota, Colombia

来源：

NAFIPS'2003: 22ND INTERNATIONAL CONFERENCE OF THE NORTH AMERICAN FUZZY INFORMATION PROCESSING SOCIETY - NAFIPS PROCEEDINGS | 2003年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents an approach for implementing center average defuzzifier by means of distributed arithmetic. This approach was applied in the design of two digital fuzzy processors, their architectures are described and compared in terms of system level organization. An automatic hardware code generation tool was used for specifying these fuzzy processors. Furthermore, they were implemented over a VirtexE(R) FPGA. Implementation results show that it is possible to obtain a processing speed up to 45 MFLIPS and reduced area cost for distributed arithmetic based parallel organized fuzzy inference systems.

引用

页码：116 / 120

页数：5

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