A Linearization Technique for Voltage-Controlled Oscillator-based ADC

In this paper, a linearization technique for voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) is presented. Even order harmonics are canceled by using pseudo-differential architecture with two identical VCO-based ADCs. The effect of cancelation technique is verified through simulation with a prototype designed in 0.18 mu m CMOS technology and verilog. The CMOS ring VCO consumes about 280 mu W of power in average and the digital counter is implemented in verilog. With the sampling frequency of 100MHz, the prototype achieves signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) of 58.2dB, 60dB and 56.5dB, respectively, when the signal bandwidth is 5MHz. Although the power consumption of the overall ADC is doubled compared to a single channel ADC, the figure-of-merit (FOM) of the ADC is improved by 2.95 times due to the SNDR improvement by linearization technique.