Analytical Model and Structure of the Multilayer Enhancement-Mode β-Ga2O3 Planar MOSFETs

In this article, the planar beta-Ga2O3 junctionless transistors with/without unintentional doping (UID) buffer layer are numerically investigated. It was found that the double-layer Ga2O3 MOSFETs (epilayer/buffer layer) show a trade-off between threshold voltage (V-th) and device reliability (resulting from anomalous Fe out-diffusion), as a function of the thickness (T-buf) and carrier concentrations (N-buf) of beta-Ga2O3 buffer layer. The simulation results show that an adequate buffer layer (200 nm < T-buf < 500 nm, N-buf < 5 x 10(14) cm(-3)) is beneficial to the pinch-off characteristic of beta-Ga2O3 planar MOSFETs. A novel triple-layer MOSFET (introducing a low-doped beta-Ga2O3 surface layer above the epilayer) is subsequently proposed and demonstrated to be an easy pathway to modulate V-th by adjusting the thickness and doping concentration of surface layer. In addition, the effect of the lateral extension N+ region is also discussed. As a result, the triple-layer beta-Ga2O3 MOSFET with an optimized dimension can achieve positive enhancement-mode and better deviceperformance: breakdown voltage (V-br) and power figures of merit (P-FOM) are improved by 173.71% and 65.37%, respectively, while specific ON- resistance is increased by 391.35%.