Die Thickness Optimization for Preventing Electro-Thermal Fails Induced by Solder Voids in Power Devices

被引：0
|
作者：
Vitello, Dario [1 ]
Albertinetti, Andrea [1 ]
Rovitto, Marco [1 ]
机构：
[1] STMicroelectronics, Via Camillo Olivetti 2, I-20864 Agrate Brianza, MB, Italy
来源：
2019 IEEE 69TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) | 2019年
关键词：
thin die; solder voids; power device; finite element method; electrical over stressfail;
D O I：
10.1109/ECTC.2019.00-34
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Vertical power devices require thin dice to reach high electrical performance especially for automotive market. Beside their several advantages, thin power devices reveal issues related to assembly processes. Die bonding process step typically generates solder voids which can lead to thermal-induced fails. The paper deals with die thickness optimization in order to reduce the risk of failures due to the presence of voids by considering manufacturing limitations. For this purpose, electro-thermal modeling is employed to calculate the temperature at which fail occurs. Further, it allows to estimate the impact of die thickness and solder void size on the device temperature distribution during operating life.
引用
收藏
页码：2091 / 2096
页数：6
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