Library-Free Synthesis for Area-Delay Minimization

With a limited number of pre-constructed gates available, current standard cell libraries are not well equipped to take full advantage of advances in deep submicron technology by implementing functions as complex gates. As reported in [1], in a technology process capable of supporting five serial MOS devices, 425,803 unique complex gates may be created - clearly much higher than what is currently available in today's cell libraries. A richer cell library allows the technology mapper more freedom to better select matches to reduce area, delay and power consumption. This paper proposes a novel algorithm for mapping an input netlist to a library of virtual cells by minimizing logical effort delay to select a gate architecture which minimizes the design area-delay product. Initial simulation results show an average of 59.95% reduction in transistor count, 44.75% reduction in circuit overall area, 40.06% reduction in area-delay product, at a cost of a 3.4% increase in delay by applying this algorithm to standard benchmark circuits compared to results obtained from Synopsys Design Compiler with high map effort for delay minimization.