A microprocessor architecture utilizing histories of dynamic sequences saved in distributed memories

被引：0
|
作者：
Sato, T
机构：
[1] Toshiba Corp, Kawasaki-shi, Japan
来源：
IEICE TRANSACTIONS ON ELECTRONICS | 1998年 / E81C卷 / 09期
关键词：
instruction level parallelism; superscalar processors; out-of-order execution; non-consecutive basic block buffer; dynamic speculation of data dependence;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In order to improve microprocessor performance, we propose to utilize histories of dynamic instruction sequences. A lot of special purpose memories integrated in a processor chip hold the histories. In this paper, we describe the usefulness of using two special purpose memories: Non-Consecutive basic block Buffer (NCB) and Reference Prediction Table (RPT). The NCB improves instruction fetching efficiency in order to relieve control dependences. The RPT predicts data addresses in order to speculate data dependences. From the simulation study, it has been Found that the proposed mechanisms improve processor performance by up to 49.2%.
引用
收藏
页码：1398 / 1407
页数：10
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