A microprocessor architecture utilizing histories of dynamic sequences saved in distributed memories

被引：0
|
作者：
Sato, T
机构：
[1] Toshiba Corp, Kawasaki-shi, Japan
来源：
IEICE TRANSACTIONS ON ELECTRONICS | 1998年 / E81C卷 / 09期
关键词：
instruction level parallelism; superscalar processors; out-of-order execution; non-consecutive basic block buffer; dynamic speculation of data dependence;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In order to improve microprocessor performance, we propose to utilize histories of dynamic instruction sequences. A lot of special purpose memories integrated in a processor chip hold the histories. In this paper, we describe the usefulness of using two special purpose memories: Non-Consecutive basic block Buffer (NCB) and Reference Prediction Table (RPT). The NCB improves instruction fetching efficiency in order to relieve control dependences. The RPT predicts data addresses in order to speculate data dependences. From the simulation study, it has been Found that the proposed mechanisms improve processor performance by up to 49.2%.
引用
收藏
页码：1398 / 1407
页数：10
相关论文
共 50 条
  • [1] A Microprocessor Protection Architecture against Hardware Trojans in Memories
    Bolat, Alperen
    Cassano, Luca
    Reviriego, Pedro
    Ergin, Oguz
    Ottavi, Marco
    2020 15TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA (DTIS 2020), 2020,
  • [2] A Microprocessor Protection Architecture against Hardware Trojans in Memories
    Bolat, Alperen
    Cassano, Luca
    Reviriego, Pedro
    Ergin, Oguz
    Ottavi, Marco
    Proceedings - 2020 15th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2020, 2020,
  • [3] DYNAMIC CONTROL OF ACCELERATOR SYSTEMS UTILIZING MICROPROCESSOR TECHNOLOGY
    MALONE, HF
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1983, 30 (02) : 1511 - 1513
  • [4] Performance Evaluation of Modern Broadwell Architecture of a Parallel & Distributed Microprocessor
    Saeed, Kanwal
    Raja, Gulistan
    2017 INTERNATIONAL SYMPOSIUM ON WIRELESS SYSTEMS AND NETWORKS (ISWSN), 2017,
  • [5] Generating checking sequences for a distributed test architecture
    Ural, H
    Williams, C
    TESTING OF COMMUNICATING SYSTEMS, PROCEEDINGS, 2003, 2644 : 146 - 162
  • [6] A Master-Slave Distributed Power Management Architecture for Dynamic Voltage and Frequency Scaling (DVFS) for Low Power Microprocessor
    Chen, Yen-Ming
    Chen, Ching-Jan
    Chao, Yu-Lin
    2024 IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION, APEC, 2024, : 1900 - 1904
  • [7] An architecture for feature detection utilizing dynamic synapses
    Heittmann, A
    Ramacher, U
    2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS, 2004, : 373 - 376
  • [8] HARDWARE ARCHITECTURE FOR A DISTRIBUTED MICROPROCESSOR-BASED CHROMATOGRAPHY LABORATORY AUTOMATION SYSTEM
    GAY, HP
    MILLER, LA
    LEUNG, AT
    ABSTRACTS OF PAPERS OF THE AMERICAN CHEMICAL SOCIETY, 1976, 172 (SEP3): : 19 - 19
  • [9] DISTRIBUTED MICROPROCESSOR ARCHITECTURE FOR FIXED AND MOBILE ACOUSTIC ARRAY ADAPTIVE BEAM FORMING
    RAMSEYER, RR
    MORGERA, SD
    IEEE JOURNAL OF OCEANIC ENGINEERING, 1979, 4 (02) : 46 - 51
  • [10] Utilizing architecture models for secure distributed web applications and services
    Wild, Stefan
    Gaedke, Martin
    IT-INFORMATION TECHNOLOGY, 2014, 56 (03): : 112 - 118
12345