Simulation based feasibility study of Junction Vertical Slit Field-Effect Transistor (JVeSFET)

被引：0
|
作者：
Pfitzner, Andrzej [1 ]
Staniewski, Michal [2 ]
Strzyga, Michal [2 ]
机构：
[1] Warsaw Univ Sci & Technol, Inst Mikroelekt & Optoelekt, PL-00662 Warsaw, Poland
[2] Warsaw Univ Sci & Technol, Wydzial Elekt & Tech Informacyjnych, PL-00662 Warsaw, Poland
来源：
PRZEGLAD ELEKTROTECHNICZNY | 2010年 / 86卷 / 11A期
关键词：
JFET; Vertical-Slit Transistor Integrated Circuit; JVeSFET; SOI TECHNOLOGY;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents simulated DC characteristics of deep-submicron JFETs conforming to the principle of extreme layout regularity, that is a foundation of a new Vertical Slit geometry ICs (VeSTICs) vision proposed in [4]. Exploration of parameter space of this fully symmetrical dual gate JVeSFETs has been performed. As a conclusion an assessment of applicability of these devices in nano-size era SoCs is proposed.
引用
收藏
页码：59 / 63
页数：5
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