A low voltage design technique for low noise RF integrated Circuits

Analysis and optimization of the bias conditions and noise parameters of MOS devices are presented. A design technique based on a narrowband LC-folded cascode topology is proposed for low voltage RF integrated Circuits. The technique is applied to the design of a 1V LNA operating at 1.9 GHz using a 0.5 mu m CMOS technology. Simulation results show that the LNA provide a noise figure of 1.7 dB, gain of 10 dB, and is well matched at the input. The LNA also provides a minimum noise figure of 1.6 dB.