Symbolic Execution of Programmable Logic Controller Code

被引:21
|
作者
Guo, Shengjian [1 ]
Wu, Meng [1 ]
Wang, Chao [2 ]
机构
[1] Virginia Tech, Blacksburg, VA 24061 USA
[2] Univ Southern Calif, Los Angeles, CA USA
基金
美国国家科学基金会;
关键词
Symbolic execution; Test generation; Partial order reduction; Programmable logic controller; PLC; SCADA; VERIFICATION;
D O I
10.1145/3106237.3106245
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
Programmable logic controllers (PLCs) are specialized computers for automating a wide range of cyber-physical systems. Since these systems are often safety-critical, software running on PLCs need to be free of programming errors. However, automated tools for testing PLC software are lacking despite the pervasive use of PLCs in industry. We propose a symbolic execution based method, named SYMPLC, for automatically testing PLC software written in programming languages specified in the IEC 61131-3 standard. SYMPLC takes the PLC source code as input and translates it into C before applying symbolic execution, to systematically generate test inputs that cover both paths in each periodic task and interleavings of these tasks. Toward this end, we propose a number of PLC-specific reduction techniques for identifying and eliminating redundant interleavings. We have evaluated SYMPLC on a large set of benchmark programs with both single and multiple tasks. Our experiments show that SYMPLC can handle these programs efficiently, and for multi-task PLC programs, our new reduction techniques outperform the slate-of-the-art partial order reduction technique by more than two orders of magnitude.
引用
收藏
页码:326 / 336
页数:11
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