Impact of VLSI Design Techniques on Implementation of Parallel Prefix Adders

Adder in general is a digital block used to perform addition operation of given data and generates the results as sum and carry_out. This block is used in various platform for addition/subtraction/multiplication applications. There are several approaches to design and verify the functionality of the adder, based on which they may be classified on type of data it uses for addition, precession of the adder, algorithm used to implementation the adder structure. In this paper we are concentrating on the algorithm/method used to implement an adder structure while keeping the precision constant and considering the binary data for verification of the design. Use of conventional adders like ripple carry adder, carry save adder and carry look ahead adder are not used/implemented for industry and research applications, on the other hand the parallel prefix adders became popular with their fast carry generation network. The presented work gives a detailed analysis on the impact of various VLSI Design techniques like CMOS, GDI, PTL, and modified GDI techniques to implement the parallel prefix adders like Kogge Stone Adder (KSA), Brent Kung Adder (BKA) and Lander Fischer Adder with precession of 4bits, 8bits and 16bits. To measure the performance (in terms of Number of Transistors required, Power Consumed, and Speed) and verify the functionality of these adders we have used Cadence Design Suite 6.1.6 tool with GPDK 180 nm MOS technology, from the results and comparative analysis we can observe that the CMOS technique consumes less power and more transistors to implement a logic, whereas the GDI technique consumes slightly more power than CMOS and implements the logic with less number of transistors. In this paper we also present a simple approach to get the best of both techniques by new technique as modified GDI technique, using this we have optimized the design both in terms of power and transistors used.