On-line detection of faults in carry-select adders

被引：0

作者：

Kumar, BK ^{[1
]}

Lala, PK ^{[1
]}

机构：

[1] Univ Arkansas, Dept Comp Sci & Comp Engn, Fayetteville, AR 72701 USA

来源：

INTERNATIONAL TEST CONFERENCE 2003, PROCEEDINGS | 2003年

关键词：

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

This paper proposes an architecture for implementing a self-checking 4-bit carry select adder that can be extended to any n-bit addition. The overhead is directly proportional to the number of transistors in the adder.

引用

页码：912 / 918

页数：7

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