Real-Time Digital Modulation Classification Based on Support Vector Machines

In this paper we investigate the use of the Support Vector Machine (SVM) approach to develop simple and efficient VLSI architectures for real-time digital modulation classification. Such simplicity and efficiency arise from the adoption of a front end block that is based on histograms. Particularly, we compare two decision schemes to solve the multiclass classification problem with linear SVMs, Pairwise and One Against the Rest (OAR), and propose an enhanced OAR scheme to improve the hit rate for low SNR values. Dedicated VLSI architectures for the three schemes were developed and logically synthesized with an industrial standard-cell flow for a 90 nm library. Functional simulation results show that the Enhanced-OAR verifier achieves up to 76% of hit rate in the 0 to 5 dB range, which corresponds to accuracy improvements of up to 162% over the OAR classifier. Synthesis results indicate a 21.8% of area overhead and 2% of power and energy increases. The results also pointed out that the Enhanced-OAR classifier is 14.1% smaller, consumes 30.1% less power and is 30.2% more energy-efficient than the Pairwise classifier, while providing up to 58.3% of accuracy improvements.