VLSI Architectures for Digital Modulation Classification using Support Vector Machines

This paper presents VLSI architectures to perform Digital Modulation Classification based on Support Vector Machines. In order to obtain suitably small circuitry, the designed architectures use a recently proposed front end that is based on histograms. Four versions of classifier architectures were modeled in Verilog and synthesized for a 90 nm commercial standard cells library, two of them using the pairwise and two with the one against rest (OAR) multiclass classification schemes. Synthesis results showed that the OAR are 32.7% smaller, consume 32% less power and are 32% more energy-efficient than the pairwise classifiers, while achieving the same accuracy.