A 93.4-to-104.8 GHz 57 mW Fractional-N Cascaded Sub-Sampling PLL with True In-Phase Injection-Coupled QVCO in 65 nm CMOS

被引：0

作者：

Yi, Xiang ^{[1
]}

Liang, Zhipeng ^{[1
]}

Feng, Guangyin ^{[1
]}

Boon, Chirn Chye ^{[1
]}

Meng, Fanyi ^{[1
]}

机构：

[1] Nanyang Technol Univ, VIRTUS, Singapore, Singapore

来源：

2016 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC) | 2016年

关键词：

CMOS voltage-controlled oscillator (VCO); TIPIC quadrature VCO (QVCO); low phase noise; phase-locked loop (PLL); sub-sampling PLL; frequency synthesizer; millimetre wave (mm-Wave); W-band;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fully integrated 93.4-to-104.8 GHz 57 mW cascaded PLL, with true in-phase injection-coupled QVCO, occupies 0.88 mm(2) in 65 nm CMOS. By cascading the fractional-N PLL and the sub-sampling PLL, good phase noise, high resolution and wide acquisition range are achieved simultaneously. The measured phase noise of QVCO and PLL are -112.67 and -108.75 dBc/Hz at 10 MHz offset, respectively. The FOM and FOMT of the QVCO at 10 MHz offset are -177.5 and -179.0 dBc/Hz, respectively.

引用

页码：122 / 125

页数：4

共 16 条

[1] A 93.4-104.8-GHz 57-mW Fractional-N Cascaded PLL With True In-Phase Injection-Coupled QVCO in 65-nm CMOS Technology
Yi, Xiang
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[2] A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology
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[3] A 57.9-to-68.3GHz 24.6mW Frequency Synthesizer with In-Phase Injection-Coupled QVCO in 65nm CMOS
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