2-Dilated flattened butterfly: A nonblocking switching topology for high-radix networks

被引:6
|
作者
Thamarakuzhi, Ajithkumar [1 ]
Chandy, John A. [1 ]
机构
[1] Univ Connecticut, Dept Elect & Comp Engn, Storrs, CT 06269 USA
基金
美国国家科学基金会;
关键词
Switch topologies; Nonblocking networks;
D O I
10.1016/j.comcom.2011.05.002
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
High-performance computing is highly dependent on the communication network connecting the nodes. In this paper, we propose a 2-Dilated flattened butterfly (2DFB) network which provides non-blocking performance for relatively low cost overhead. We study the topological properties of the proposed 2DFB network and compare it with different nonblocking switching topologies. We observe that a dilation factor of two is sufficient to obtain nonblocking property for a flattened butterfly structure irrespective of its size or dimension. Dilating each link in a flattened butterfly causes an increase in cost. Therefore, we modeled the implementation cost of a 2DFB network and compared it with other popular nonblocking networks. We observe that the cost of a 2DFB is less than other nonblocking networks, while at the same time providing reduced latency because of its reduced diameter and hop count. We also propose a procedure to develop a conflict-free static routing schedule as well as an adaptive load balanced routing scheme (ALDFB) for 2DFB networks. Finally, we also describe the hardware implementation of a 2DFB network using the NetFPGA as the switching element and verify the nonblocking behavior of a 2DFB. We also show that the 2DFB topology can be used to build high speed switching systems with reduced cost. (C) 2011 Elsevier B.V. All rights reserved.
引用
收藏
页码:1822 / 1835
页数:14
相关论文
共 37 条
  • [1] Design and Implementation of a Nonblocking 2-Dilated Flattened Butterfly Switching Network
    Thamarakuzhi, A.
    Chandy, J. A.
    [J]. IEEE LATIN AMERICA TRANSACTIONS, 2011, 9 (04) : 557 - 564
  • [2] Flattened Butterfly : A Cost-Efficient Topology for High-Radix Networks
    Kim, John
    Dally, William J.
    Abts, Dennis
    [J]. ISCA'07: 34TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, CONFERENCE PROCEEDINGS, 2007, : 126 - 137
  • [3] Adaptive Load Balanced Routing for 2-Dilated Flattened Butterfly Switching Network
    Thamarakuzhi, Ajithkumar
    Chandy, John A.
    [J]. PROCEEDINGS OF THE TENTH INTERNATIONAL CONFERENCE ON NETWORKS (ICN 2011), 2011, : 139 - 144
  • [4] High-Radix Nonblocking Integrated Optical Switching Fabric for Data Center
    Wang, Zhifei
    Xu, Jiang
    Yang, Peng
    Wang, Zhehui
    Duong, Luan Huu Kinh
    Chen, Xuanqi
    [J]. JOURNAL OF LIGHTWAVE TECHNOLOGY, 2017, 35 (19) : 4268 - 4281
  • [5] High-radix Packet-Switching Architecture for Data Center Networks
    Hassen, Fadoua
    Mhamdi, Lotfi
    [J]. 2017 IEEE 18TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE SWITCHING AND ROUTING (IEEE HPSR), 2017,
  • [6] Flattened butterfly topology for on-chip networks
    Kim, John
    Balfour, James
    Dally, William J.
    [J]. MICRO-40: PROCEEDINGS OF THE 40TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, 2007, : 172 - +
  • [7] High-Radix On-chip Networks with Low-Radix Routers
    Jain, Animesh
    Parikh, Ritesh
    Bertacco, Valeria
    [J]. 2014 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2014, : 289 - 294
  • [8] An Efficient Label Routing on High-Radix Interconnection Networks
    Lei, Fei
    Dong, Dezun
    Liao, Xiangke
    [J]. 2017 IEEE 23RD INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS (ICPADS), 2017, : 596 - 603
  • [9] Dynamic Global Adaptive Routing in High-Radix Networks
    Kasan, Hans
    Kim, Gwangsun
    Yi, Yung
    Kim, John
    [J]. PROCEEDINGS OF THE 2022 THE 49TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA '22), 2022, : 771 - 783
  • [10] SCOC: High-Radix Switches Made of Bufferless Clos Networks
    Chrysos, Nikolaos
    Minkenberg, Cyriel
    Rudquist, Mark
    Basso, Claude
    Vanderpool, Brian
    [J]. 2015 IEEE 21ST INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA), 2015, : 402 - 414