Electron transport in silicon-on-insulator nanodevices

We have studied the electron transport properties of two sets of Silicon on Insulator (SOI) nanodevices: i) quantum-well based devices where carriers are quantized in one dimension (1D) and ii) quantum-wire based devices, where carriers are quantized in two dimensions (2D). In the first group, namely quantum-well based devices, the electron mobility dependence on the silicon thickness, T-w in double-gate SOI devices was compared with that in Single-Gate SOI structures. Thus, we determined the existence of a range of silicon layer thicknesses in which electron mobility in DGSOI inversion layers is significantly improved as compared to bulk-silicon or SGSOI inversion layers, due to the volume inversion effect. We have also shown that electron mobility is greatly improved in strained Si/SiGe-OI devices, in comparison with unstrained SOI devices. We can conclude that strained-Si/SiGe-on-Insulator inversion layers efficiently combine the improved mobility of strained-Si/SiGe devices with the advantages offered by SOI devices. With regard to quantum-wire based devices, we have analyzed the phonon-limited mobility in silicon quantum wires by means of a one-particle Monte Carlo simulator. It has been observed that an increase of the phonon scattering produces a noticeable reduction of the electron mobility observed when the device dimensions are reduced. Therefore, we have observed that the transition from 2D to 1D electron gas produces a degradation of the electron transport properties.