Hardware/software partitioning and scheduling algorithm based on FPGA

被引：0
|
作者：
Li, Lanying [1 ]
Chen, Longjuan [1 ]
机构：
[1] Harbin Univ Sci & Technol, Coll Comp Sci & Technol, Harbin 150080, Peoples R China
来源：
2014 7TH CONFERENCE ON CONTROL AND AUTOMATION (CA) | 2014年
关键词：
low power consumption; heterogeneous multi-core processor; hardware/software partitioning;
D O I：
10.1109/CA.2014.11
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
For low power consumption of system structure in embedded heterogeneous multi-core processor, decompose the hardware/software partitioning into task partitioning and low power scheduling in two stages. The algorithm of reducing power consumption is adopted at each stage, and finally optimal algorithm of two stages will be integrated in order to achieve the system goal of maximum reduction of the power consumption.
引用
收藏
页码：15 / 18
页数：4
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