A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI

被引：0

作者：

Nouripayam, Masoud ^{[1
]}

Rodrigues, Joachim ^{[1
]}

Luo, Xiao ^{[2
]}

Johansson, Tom ^{[2
]}

Mohammadi, Babak ^{[2
]}

机构：

[1] Lund Univ, Dept Elect & Informat Technol, S-22100 Lund, Sweden

[2] Xenergic AB, Scheelevagen 15, S-22370 Lund, Sweden

来源：

ESSCIRC 2021 - IEEE 47TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC) | 2021年

基金：

欧盟地平线“2020”;

关键词：

SRAM; dual-port; boost-assist; low-voltage; low-power; 6T bitcell; single-ended read;

D O I：

10.1109/ESSCIRC53450.2021.9567785

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 32 Kb dual-port low-voltage SRAM in 28 nm FD-SOI, featuring foundry supplied high-density 6T bitcells, is presented. Dual-port configurability is realized by a unique dual-rail architecture, utilizing boost techniques that guarantee reliable operation in low-voltage. The area cost of the array is 62% lower, compared to widely used 8T two-port or dual-port SRAM arrays. The SRAM reliably operates in the low-voltage regime, and an access rate of 1 MHz is measured at V-MIN of 0.29 V. The highest energy efficiency of 135U/bit-access is obtained at 80 MHz access rate, at a V-DD of 0.54 V.

引用

页码：459 / 462

页数：4

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