WiDir: A Wireless-Enabled Directory Cache Coherence Protocol

被引:9
|
作者
Franques, Antonio [1 ]
Kokolis, Apostolos [1 ]
Abadal, Sergi [2 ]
Fernando, Vimuth [1 ]
Misailovic, Sasa [1 ]
Torrellas, Josep [1 ]
机构
[1] Univ Illinois, Champaign, IL USA
[2] Univ Politecn Cataluna, Barcelona, Spain
关键词
Multicore; Wireless Network on chip; Directory cache coherence protocol; MILLIMETER-WAVE; 65-NM CMOS; CHANNEL; PERFORMANCE; NETWORKS; NOC; ARCHITECTURE;
D O I
10.1109/HPCA51647.2021.00034
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
As the core count in shared-memory manycores keeps increasing, it is becoming increasingly harder to design cache-coherence protocols that deliver high performance without an inordinate increase in complexity and cost. In particular, sharing patterns where a group of cores frequently reads and writes a shared variable are hard to support efficiently. Hence, programmers end up tuning their applications to avoid these patterns, hurting the programmability of shared memory. To address this problem, this paper uses the recently-proposed on-chip wireless network technology to augment a conventional invalidation-based directory cache coherence protocol. We call the resulting protocol WiDir. WiDir seamlessly transitions between wired and wireless coherence transactions for a given line based on the access patterns in a programmer-transparent manner. In this paper, we describe the protocol transitions in detail. Further, an evaluation using SPLASH and PARSEC applications shows that WiDir substantially reduces the memory stall time of applications. As a result, for 64-core runs, WiDir reduces the execution time of applications by an average of 22% compared to a conventional directory protocol. Moreover, WiDir is more scalable. These benefits are obtained with a very modest power cost.
引用
收藏
页码:304 / 317
页数:14
相关论文
共 50 条
  • [31] Cache memory coherence protocol for distributed systems
    Aguilar Castro, Jose Lisandro
    Sumoza Matos, Rodolfo Leonardo
    REVISTA TECNICA DE LA FACULTAD DE INGENIERIA UNIVERSIDAD DEL ZULIA, 2007, 30 (02): : 170 - 178
  • [32] Relaxing cache coherence protocol with QOLB synchronizations
    Lee, JB
    Jhon, CS
    HIGH PERFORMANCE COMPUTING ON THE INFORMATION SUPERHIGHWAY - HPC ASIA '97, PROCEEDINGS, 1997, : 1 - 6
  • [33] A cache coherence protocol for distributed memory platforms
    Sumoza, Rodolfo
    Castro, Jose Aguilar
    COMPUTER SYSTEMS SCIENCE AND ENGINEERING, 2010, 25 (05): : 343 - 353
  • [34] An adaptive limited pointers directory scheme for cache coherence of scalable multiprocessors
    Park, CH
    Choi, JH
    Park, KH
    Park, D
    EURO-PAR'99: PARALLEL PROCESSING, 1999, 1685 : 753 - 756
  • [35] SelectDirectory: A Selective Directory for Cache Coherence in Many-Core Architectures
    Yao, Yuan
    Wang, Guanhua
    Ge, Zhiguo
    Mitra, Tulika
    Chen, Wenzhi
    Zhang, Naxin
    2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2015, : 175 - 180
  • [36] VERIFICATION OF THE FUTUREBUS+ CACHE COHERENCE PROTOCOL
    CLARKE, EM
    GRUMBERG, O
    HIRAISHI, H
    JHA, S
    LONG, DE
    MCMILLAN, KL
    NESS, LA
    FORMAL METHODS IN SYSTEM DESIGN, 1995, 6 (02) : 217 - 232
  • [37] A cache coherence protocol for distributed memory platforms
    Sumoza, Rodolfo
    Aguilar Castro, Jose
    COMPUTER SYSTEMS SCIENCE AND ENGINEERING, 2011, 26 (01): : 13 - 23
  • [38] SHARED BLOCK CONTENTION IN A CACHE COHERENCE PROTOCOL
    DUBOIS, M
    WANG, JC
    IEEE TRANSACTIONS ON COMPUTERS, 1991, 40 (05) : 640 - 644
  • [39] A Dual-Consistency Cache Coherence Protocol
    Ros, Alberto
    Jimborean, Alexandra
    2015 IEEE 29TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM (IPDPS), 2015, : 1119 - 1128
  • [40] Relaxing cache coherence protocol with QOLB synchronizations
    Lee, Jae Bum
    Jhon, Chu Shik
    Proceedings of the Conference on High Performance Computing on the Information Superhighway, HPC Asia'97, 1997, : 1 - 6