Design and Analysis of a Low-Power Ternary SRAM

被引：0

作者：

Choi, Youngchang ^{[1
]}

Kim, Sunmean ^{[2
]}

Lee, Kyongsu ^{[1
]}

Kang, Seokhyeong ^{[1
]}

机构：

[1] POSTECH, Dept Elect Engn, Pohang, South Korea

[2] POSTECH, Inst Artificial Intelligence, Pohang, South Korea

来源：

2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2021年

基金：

新加坡国家研究基金会;

关键词：

LOGIC;

D O I：

10.1109/ISCAS51556.2021.9401259

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes the design of a ternary inverter that uses low current as input voltage is VDD/2. When the supply voltage is set to 1 V, current supplied by a voltage source as an input voltage VDD/2 is reduced by 22.75% from 1.89 mu A to 1.46 mu A. By connecting ternary inverters back-to-back, a trit-storage element is implemented as a ternary SRAM cell. This paper also presents the first verification of read/write schemes that consider noise margins.

引用

页数：4

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