Enhancement mode p-channel SnO thin-film transistors with dual-gate structures

被引:11
|
作者
Choi, Yong-Jin [1 ]
Han, Young-Joon [1 ]
Jeong, Chan-Yong [1 ]
Song, Sang-Hun [1 ]
Baek, Geun Woo [2 ]
Jin, Sung Hun [2 ]
Kwon, Hyuck-In [1 ]
机构
[1] Chung Ang Univ, Sch Elect & Elect Engn, Seoul 156756, South Korea
[2] Incheon Natl Univ, Dept Elect Engn, Inchon 406772, South Korea
来源
基金
新加坡国家研究基金会;
关键词
BIAS STRESS STABILITY; DEPOSITION; TFT;
D O I
10.1116/1.4923236
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The authors demonstrate the enhancement mode p-type SnO thin-film transistors (TFTs) using dual gate (DG) structures. The cross-linked polyvinyl alcohol dielectric with a polymethylmethacrylate buffer layer is formed as a top gate (TG) insulator of the DG SnO TFT. The fabricated DG SnO TFT exhibits better electrical performances than the bottom gate (BG) and TG SnO TFTs including higher field-effect mobility and smaller subthreshold slope. In fabricated DG TFTs, the threshold voltage (V-th) of the BG TFT is linearly modulated by the voltage applied to the TG electrode. The BG transfer curve exhibits a depletion mode operation when measured while TG is grounded, but operates in the enhancement mode with a negative V-th (= -0.9 V) when a positive bias of 10 V is applied to the TG electrode. The enhancement mode operation of p-type SnO TFTs can increase the output voltage swing range and decreases the off-stage leakage currents of the complementary logic circuits. (C) 2015 American Vacuum Society.
引用
收藏
页数:5
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