Warpage of thin wafers using computer aided reflection moire method

To cope with advances in the electronic packaging industry, thinner wafers are being widely employed to produce thinner packages. However, this has lead to an increase in random cracks during the wafer singulation process, thus reducing the yield of the overall production. Large stresses are induced particularly during backside metal deposition. The wafers bend due to these stresses. This residual stress due to warpage lead to cracks which will severely re-orient the residual stress distributions, thus, weakening the mechanical and electrical properties of the singulated die. In this study, Computer aided reflection moire technique is adapted to further investigates the warpage induced on wafers with different backside metallization (bare silicon, AuY, AuX). The backside metal on the wafer is then etched to remove the residual stress. Residual stress due to the effect of warpage caused by different backside metallization has been experimentally investigated and compared. Applicability of this technique to correlate with the random crack in the die is further validated.