A quarter pel full search block motion estimation architecture for H.264/AVC

被引：5
|
作者：
Rahman, CA [1 ]
Badawy, W [1 ]
机构：
[1] Univ Calgary, Lab Integrated Video Syst, Calgary, AB T2N 1N4, Canada
来源：
2005 IEEE International Conference on Multimedia and Expo (ICME), Vols 1 and 2 | 2005年
关键词：
D O I：
10.1109/ICME.2005.1521448
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper presents a novel quarter pel full search block motion estimation architecture for H.264/AVC encoder. The proposed architecture is capable of calculating all 41 motion vectors required by the various size blocks, supported by H.264/AVC, in parallel. The architecture has been prototyped in Verilog HDL, simulated and synthesized for Xilinx Virtex2 FPGA. The experimental result shows that the architecture is capable of processing CIF frame sequences in real time considering 5 reference frames within the search range of -3.75 to +4.00 at a clock speed of 120MHz. The maximum speed of the architecture is around 150MHz.
引用
收藏
页码：414 / 417
页数：4
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