Using duplication with compare for on-line error detection in FPGA-based designs

It is well known that SRAM-based FPGAs are susceptible to single-event upsets (SEUs) in radiation environments. A variety of mitigation strategies have been demonstrated to provide appropriate mitigation and correction of SEUs in these environments. While full mitigation of SEUs is appropriate for some situations, some systems may tolerate SEUs as long as these upsets are detected quickly and correctly. These systems require effective error detection techniques rather than costly error correction methods. This work leverages a well-known error detection technique for FPGAs called duplication with compare (DWC). This technique has been shown to be very effective at quickly and accurately detecting SEUs using fault injection and radiation testing.