An On-Chip Static and Dynamic DAC Error Correction Technique for High Speed Multibit Delta-Sigma Modulators

This paper presents an on-chip technique for calibrating static and dynamic DAC errors in a multibit continuous-time (CT) Delta-Sigma (Delta Sigma) modulator. Dynamic errors such as inter-symbol-interference (ISI) affect the DAC output at every data transition and significantly deteriorate the in-band noise floor in high-speed applications. In the proposed technique, a compensation current is injected in the loop at every up-transition of input data to cancel the ISI error of each unit cell, thus improving its dynamic linearity. High linearity merged-input -feedback Gm-C integrators have been shown to enhance the converter's linearity and reduce power but require that the feedback DAC common mode matches the input-signal common mode. A biasing circuit for the current-steering feedback DAC is proposed to match its output common mode to the input signal common mode across PVT. Simulation results for a 70 MHz bandwidth, 3rd order modulator, operating at a 2.8 GHz sampling rate, show a 2.8dB improvement in the in-band noise with the proposed dynamic calibration technique as well as maintaining the common-mode matching requirements across PVT.