A Dual-Mode VCO based Low-Power Synthesizer with Optimized Automatic Frequency Calibration for Software-Defined Radio

被引：0

作者：

Zhou, Jin ^{[1
]}

Li, Wei ^{[1
]}

Huang, Deping ^{[1
]}

Lian, Chen ^{[1
]}

Li, Ning ^{[1
]}

Ren, Junyan ^{[1
]}

机构：

[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai 201203, Peoples R China

来源：

2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2011年

关键词：

CMOS; RECEIVER; GHZ; PLL;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low power sigma-delta fractional-N frequency synthesizer for software-defined radio (SDR) implemented in a 0.13 mu m CMOS process is presented, based on a dual-mode VCO (DMVCO) reconfigurable between wideband mode and quadrature mode, with optimized automatic frequency calibration (AFC). The proposed optimized AFC enables a more accurate band selection as well as a lower power for a dual-VCO PLL. A multi-phase counter (MPC) accelerates the calibration process without ruining the calibration accuracy. Simulated phase noise is -123dBc/Hz at 1MHz offset from a 1.8GHz carrier. The spectral purity is better than 45dBc from the output of mixer. The locking time of PLL is about 40 mu s with an AFC time less than 10 mu s. The 0.4-6GHz synthesizer consumes only 35mW to 51mW from a 1.2V supply.

引用

页码：1145 / 1148

页数：4

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