A Dual-Mode VCO based Low-Power Synthesizer with Optimized Automatic Frequency Calibration for Software-Defined Radio

A low power sigma-delta fractional-N frequency synthesizer for software-defined radio (SDR) implemented in a 0.13 mu m CMOS process is presented, based on a dual-mode VCO (DMVCO) reconfigurable between wideband mode and quadrature mode, with optimized automatic frequency calibration (AFC). The proposed optimized AFC enables a more accurate band selection as well as a lower power for a dual-VCO PLL. A multi-phase counter (MPC) accelerates the calibration process without ruining the calibration accuracy. Simulated phase noise is -123dBc/Hz at 1MHz offset from a 1.8GHz carrier. The spectral purity is better than 45dBc from the output of mixer. The locking time of PLL is about 40 mu s with an AFC time less than 10 mu s. The 0.4-6GHz synthesizer consumes only 35mW to 51mW from a 1.2V supply.