A 270-GHz Fully-Integrated Frequency Synthesizer in 65nm CMOS

被引：0
|
作者：
Liu, Xiaolong [1 ]
Luong, Howard C. [1 ]
机构：
[1] Hong Kong Univ Sci & Technol, Hong Kong, Peoples R China
来源：
2019 SYMPOSIUM ON VLSI CIRCUITS | 2019年
关键词：
D O I：
10.23919/vlsic.2019.8777982
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A fully-integrated sub-THz frequency synthesizer is proposed leveraging an RF sub-sampling PLL (SS-PLL) cascaded with an ILFM-based mm-Wave LO generation chain and a sub-THz mixer for frequency extension. Third-harmonic and fourth-harmonic extraction enhancement methods are proposed for the ILFMx3 and ILFMx4, respectively. A distributed biased technique is proposed to improve the linearity of the magnetic tuning sub-THz ILFMx6. In addition, a frequency tracking loop (FTL) with frequency and amplitude calibration is proposed for the ILFMs. The 65nm CMOS prototype measures a locking range from 61.2-to-100.8GHz, 122.4-to-136.8GHz, and 198.5-to-273.60Hz, phase noise from-79.3dBc/Hz to-95.4dBc/Hz at 1-MHz offset, an integrated jitter from 124fs to 159fs, and an output power of-11dBm and DC-to-RE efficiency of 0.16% at a carrier of 211.4GHz.
引用
收藏
页码：C40 / C41
页数：2
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