Double-Pumping the Interconnect for Area Reduction in Coarse-Grained Reconfigurable Arrays

We consider double-pumped interconnect as a means of area reduction in coarse-grained reconfigurable arrays (CGRAs). Interconnect multiplexers comprise a considerable portion ()I' CGRA area. We apply double-pumping to halve the word-width of the interconnect multiplexers, saving area. The interconnect is operated at twice the system clock frequency, where the top and bottom half-words of a value are communicated in the first and second half of a clock cycle. Several circuit-level approaches for double-pumping are considered, and evaluated in different CGRA architectures with varied interconnect richness. Area and performance consequences are assessed through a 45nm standard-cell ASIC implementation. Overall CGRA area improvements of up to 16% are observed, depending on the CGRA architecture and double-pumping implementation.