Design of Polyphase FIR Filter using Bypass Feed Direct Multiplier

被引：0

作者：

Deshmukh, Rahul M. ^{[1
]}

Keote, Rashmi ^{[2
,3
]}

机构：

[1] Yeshwantrao Chavan Coll Engn, Dept Elect, VLSI Design, Hingna Rd, Nagpur 441110, Maharashtra, India

[2] Yeshwantrao Chavan Coll Engn, Hingna Rd, Nagpur 441110, Maharashtra, India

[3] Yeshwantrao Chavan Coll Engn, Dept Elect, Nagpur, Maharashtra, India

来源：

2015 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP) | 2015年

关键词：

Area; bypass feed direct multiplier; Polyphase FIR filter; shift and add multiplier;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Multirate filter are widely used in many DSP application. Many efficient architectures are design to reduce the complexity of DSP system. Adder, Multiplier are the main fundamental blocks of filter which contributes in reduction of area, power and delay parameter of filter. This paper presents polyphase FIR filter using bypass feed direct multiplier and polyphase FIR filter using shift and add multiplier. The proposed polyphase filter is design for filter of length nine. The proposed and conventional design are simulated using Xilinx ISE 13.1 tool. On comparison, proposed design is efficient in terms of area and delay than conventional design.

引用

页码：1640 / 1643

页数：4

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