Very Wide Range Frequency Synthesizer Architecture for Avionic SDR Applications

被引:0
|
作者
Ismaili, Zakaria El Alaoui [1 ,2 ]
Ajib, Wessam [2 ]
Gagnon, Francois [1 ]
Nabki, Frederic [2 ]
机构
[1] ETS, Dept Elect Engn, Montreal, PQ, Canada
[2] Univ Quebec Montreal, Dept Comp Sci, Montreal, PQ, Canada
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中图分类号
TN [电子技术、通信技术];
学科分类号
0809 ;
摘要
This paper presents a very wide range frequency synthesizer architecture appropriate to avionic software defined radio (SDR) applications. The synthesizer generates a continuous carrier frequencies range between 187 MHz and 12 GHz that covers most of avionic communication applications. The covered range is distributed into twenty sub-bands by using a voltage controlled oscillator (VCO). The considered VCO is able to achieve a tuning range from 10 GHz to 12 GHz (18.2%) and from 7 GHz to 8.5 GHz (19.35%). It includes a capacitor bank, varactors, and switched inductors and is designed in 0.13 mu m CMOS technology. Using the advanced design system (ADS) simulation tool and SpectreRF simulator, the proposed VCO exhibits a phase noise of -125 dBc/Hz at 12 GHz and at a 10 MHz offset frequency with a power consumption of 4.1 mW. At 10 GHz, the simulated synthesizer phase noise is of -102 dBc/Hz at a 1 MHz frequency offset. In addition, the loop bandwidth of the phase locked loop (PLL) is 1.1 MHz whereas the settling time is 3.64 mu s.
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页数:5
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