Dual-mode parasitic bipolar effect in dynamic CVSL XOR circuit with floating-body partially depleted SOI devices

This paper presents a detailed study on the impact of the floating body in a partially depleted (PD) SOI MOSFET on a multi-level voltage-switch current-steering type circuit using the dynamic CVSL XOR circuit as an example. It is shown that because of the cascading, differential input configuration, symmetry, and crisscross drain connections in the circuit topology, both normal-mode and inverse-mode parasitic bipolar effect (with parasitic bipolar current flowing from the source to the drain) will be present in every cycle when the clock changes from the precharge phase to the evaluation phase. The resulting impact on the circuit operation, stability and functionality is studied. The normal-mode parasitic bipolar effect is shown to lead potentially to an erroneous logic state. The history dependency (hysteresis) and pattern dependency of the parasitic bipolar effect are discussed.