Hardware Implementation of HEVC CABAC Encoder

被引：0
|
作者：
Kim, Doohwan [1 ]
Moon, Jeonhak [1 ]
Lee, Seongsoo [1 ]
机构：
[1] Soongsil Univ, Sch Elect Engn, Seoul, South Korea
来源：
2015 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | 2015年
关键词：
HEVC; CABAC; pipeline; encoder; architecture;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
CABAC is high-compression-ratio entropy coding in HEVC, but it is difficult to be parallelized for speedup. In this paper, a pipelined HEVC CABAC architecture is proposed to increase operating frequency. The proposed CABAC encoder was implemented in 0.18um technology with 158 MHz operating frequency and 45,088 gate counts.
引用
收藏
页码：183 / 184
页数：2
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