Evolution of polymorphic self-checking circuits

被引:0
|
作者
Sekanina, Lukas [1 ]
机构
[1] Brno Univ Technol, Fac Informat Technol, Brno 61266, Czech Republic
关键词
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
This paper presents elementary circuit components which exhibit self-checking properties; however, which do not utilize any additional signals to indicate the fault. The fault is indicated by generating specific values at some of standard outputs of a given circuit. In particular, various evolved adders containing conventional as well as polymorphic gates are proposed with less than duplication overhead which are able to detect a reasonable number of stuck-at-faults by oscillations at the carry-out output when the control signal of polymorphic gates oscillates.
引用
收藏
页码:186 / 197
页数:12
相关论文
共 50 条
  • [21] A hyper optimal encoding scheme for self-checking circuits
    Lo, JC
    IEEE TRANSACTIONS ON COMPUTERS, 1996, 45 (09) : 1022 - 1030
  • [22] Implementation of BIST using Self-Checking Circuits for Multipliers
    Padharpurkar, Nishant Govindrao
    Ravi, V.
    2015 International Conference on Computing, Communication and Security (ICCCS), 2015,
  • [23] Self-checking combinational circuits with unidirectionally independent outputs
    Morosow, A
    Saposhnikov, VV
    Saposhnikov, VV
    Goessel, N
    VLSI DESIGN, 1998, 5 (04) : 333 - 345
  • [24] Automated Design of Totally Self-Checking Sequential Circuits
    Greblicki, Jerzy
    Kotowski, Jerzy
    COMPUTER AIDED SYSTEMS THEORY - EUROCAST 2009, 2009, 5717 : 98 - 105
  • [25] A method for determining whether asynchronous circuits are self-checking
    Liebelt, MJ
    Lim, CC
    PROCEEDINGS OF THE NINTH ASIAN TEST SYMPOSIUM (ATS 2000), 2000, : 472 - 477
  • [26] DESIGN OF TOTALLY SELF-CHECKING ASYNCHRONOUS MODULAR CIRCUITS
    DAVID, R
    THEVENODFOSSE, P
    JOURNAL OF DESIGN AUTOMATION & FAULT-TOLERANT COMPUTING, 1978, 2 (04): : 271 - 287
  • [27] Implementation of BIST using Self-Checking Circuits for Multipliers
    Padharpurkar, Nishant Govindrao
    Ravi, V
    2015 INTERNATIONAL CONFERENCE ON COMPUTER, COMMUNICATION AND CONTROL (IC4), 2015,
  • [28] Design of self-checking fully differential circuits and boards
    Lubaszewski, M
    Mir, S
    Kolarik, V
    Nielsen, C
    Courtois, B
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2000, 8 (02) : 113 - 128
  • [29] STRONGLY FAULT-SECURE AND STRONGLY SELF-CHECKING DOMINO-CMOS IMPLEMENTATIONS OF TOTALLY SELF-CHECKING CIRCUITS
    JHA, NK
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1990, 9 (03) : 332 - 336
  • [30] DESIGN OF SELF-CHECKING CIRCUITS FOR THE TEST DIAGNOSTICS OF COMBINATIONAL DEVICES
    SPERANSKIJ, DV
    AVTOMATIKA I VYCHISLITELNAYA TEKHNIKA, 1984, (01): : 9 - 14