Use of Irregular Topologies for the Synthesis of Networks-on-Chip

This article gives a review of existing methods of designing of networks-on-chip (NoC), based on the approach that makes the projection of the characteristic task graph on a given regular topology. The general problem of NoC synthesis is characterized. The network topology can be either specialized and selected depending on the tasks to be performed or can be known in advance, in most cases, a regular topology. The method of NoC synthesis by adjusting for a specific task is analyzed. The advantages and disadvantages of this approach and the effect, achieved by its use for various implementations of NoCs are shown. The way to improve the NoC synthesis by using predefined irregular topologies with better characteristics is proposed.