Dynamic Parallel Computing Architecture for Video Processing

被引：0
|
作者：
Bharanitharan, K. [1 ]
Paul, Anand [2 ]
Jiang, Yung-Chuan [3 ]
Wang, Jhing-Fa [3 ]
机构：
[1] Korea Univ, Dept Elect Engn, Seoul, South Korea
[2] Hanyang Univ, Dept Elect Engn, Seoul, South Korea
[3] Natl Cheng Kung Univ, Dept Elect Engn, Tainan 70101, Taiwan
来源：
JOURNAL OF INTERNET TECHNOLOGY | 2010年 / 11卷 / 06期
关键词：
Motion estimation; Video coding; Parallel processing; Parallel architecture; FPGA; SPACE EXPLORATION;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, motion estimation preprocessing algorithm is mapped onto a new dynamically parallel computing architecture, namely, the parallel computing architecture, which consists of multiple parallel units It eventually reduces the computation required for motion estimation in advance video coding A directed acyclic graph is constructed to represent the video coding algorithms comprising motion estimation This speeds up the video processing with minimum sacrifice
引用
收藏
页码：867 / 873
页数：7
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