Fully hardware based WFQ architecture for high-speed QoS packet scheduling

被引：12

作者：

McLaughlin, Kieran ^{[1
]}

Burns, Dwayne ^{[1
]}

Toal, Ciaran ^{[1
]}

McKillen, Colm ^{[1
]}

Sezer, Sakir ^{[1
]}

机构：

[1] Queens Univ Belfast, ECIT, Belfast BT3 9DT, Antrim, North Ireland

来源：

INTEGRATION-THE VLSI JOURNAL | 2012年 / 45卷 / 01期

基金：

英国工程与自然科学研究理事会;

关键词：

Fair queuing; WFQ; Packet scheduling; QoS; Traffic management; Shared buffer; FPGA; FAIR QUEUING ALGORITHMS; SWITCHED NETWORKS; IMPLEMENTATION; CIRCUIT;

D O I：

10.1016/j.vlsi.2011.01.001

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing Reduced Latency DRAM (RLDRAM) II and Quad Data Rate (QDR) II SRAM memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8 Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience. (C) 2011 Elsevier B.V. All rights reserved,

引用

页码：99 / 109

页数：11

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