A Two-Dimensional (2D) Analytical Modeling and Improved Short Channel Performance of Graded-Channel Gate-Stack (GCGS) Dual-Material Double-Gate (DMDG) MOSFET

被引:22
|
作者
Vadthiya, Narendar [1 ]
Tripathi, Shweta [1 ]
Naik, R. Bhavani Shankar [1 ]
机构
[1] Motilal Nehru Natl Inst Technol Allahabad, Dept Elect & Commun Engn, Allahabad 211004, Uttar Pradesh, India
关键词
Dual-material gate (DMG); Drain induced barrier lowering (DIBL); Double-gate (DG); Graded-channel gate-stack (GCGS); Short channel effects (SCEs); SOI MOSFET; IMPACT; RELIABILITY; DIELECTRICS; SIMULATION; ANALOG;
D O I
10.1007/s12633-017-9683-1
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
A Double-gate (DG) metal-oxide-semiconductor field effect transistor (MOSFET) is emerging device architecture in sub-nanometer regime. The performance of DG MOSFET can be ameliorated by gate and channel engineering. The concept of graded-channel gate-stack (GCGS) and dual-material (DM) are incorporated in DG MOSFET. A two-dimensional (2D) analytical surface potential model for GCGS DMDG MOSFET is developed based on the solution of Poisson's equations with appropriate boundary conditions. It has been found that analytically modeled data is in good degree of agreement with numerically simulated data. The combination of both DM and GC concept introduces a step variation in potential profile at the junction of both materials in channel region and ameliorates the short channel effects (SCEs). A suppressed subthreshold swing (SS) and drain induced barrier lowering (DIBL) has been observed in the device due to an elevated average velocity of carrier and reduced drain field effect by the use of DM and GC with GS. Further, analog/RF characteristics such as transconductance generation factor (TGF), cut-off frequency (f(T)) and transconductance frequency product (TFP) have been examined with different GS high-k dielectrics. The numerically simulated data has been extracted using 2D ATLAS device simulator.
引用
收藏
页码:2399 / 2407
页数:9
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