A Novel Hardware Architecture for Rapid Object Detection Based on Adaboost Algorithm

This paper proposed a novel hardware architecture for rapid object detection based on Adaboost learning algorithm with Haar-like features as weak classifiers. A 24x24: pipelined integral image array is introduced to reduce calculation time and eliminate the problem of the huge hardware resource consumption in integral image calculation and storage. An expansion of the integral image array is also proposed to increase the parallelism at a low cost of hardware resource consumption. These methods resulted in an optimized detection process. We further implemented the process on Xilinx XUP Virtex II Pro FPGA board, and achieved all accuracy of 91.3%, and a speed of 80 fps at clock rate of 100 MHz, for 352x288 CIF image.