Experimental evaluation of MOS-FET snubber circuit

This paper presents the analyses and the design of snubber circuits for low power dc-dc converters realized with MOS-FETs. The analyses and the design procedure are based on experimental evaluation. The appropriate usage of the snubber circuit can increase the power range of the low-power dc-dc converters available as integrated circuit. The evaluation of snubber circuit is based on experimental results and its approximation. For approximation purposes the method based on differential evolution algorithm has been used. This method enables that the power transistor dissipation can be 30% lower in the case that the efficiency of converter not changes. Benefits, drawbacks and limits of the proposed approach are detailed and studied. Experimental results, obtained from boost laboratory prototype converter are reported.