The Energy Optimization for Architectures with Limited Addressing Modes Using Scratch-Pad Memory

Low power design plays a very important role in the modern embedded system Compared with traditional cache, many researchers focus on the substitute Scratch-pad memory, which can reduce energy consumption and guarantee the overall performance However, few of these optimization schemes took architectures with limited addressing modes into consideration, which means ignoring the long-branch overheads existing in almost all of Reduced instruction set computer (RISC) architectures This paper implements two matrices to illustrate those overheads quantitatively, and eventually figures out, in virtue of our improved knapsack algorithm and its corresponding dynamic programming, the most optimized image layout for energy considerations Compared with general SPM optimization method, experiments achieve up to 58 6% and average 19 5% decrease in energy consumption without any performance degradation when SPM size is only 8kbytes