Impact of a process variation on nanowire and nanotube device performance

被引:81
|
作者
Paul, Bipul C. [1 ]
Fujita, Shinobu
Okajima, Masaki
Lee, Thomas H.
Wong, H.-S. Philip
Nishi, Yoshio
机构
[1] Stanford Univ, Ctr Integrated Syst, Stanford, CA 94305 USA
[2] Toshiba Amer Res Inc, San Jose, CA 95131 USA
关键词
CNFET performance under variation; nanowire FET performance under variation; process variation;
D O I
10.1109/TED.2007.901882
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we present an in-depth analysis of the nanowire and nanotube device performance under process variability. Although every process parameter variation drastically affects the conventional MOSFET performance, we found that nanowire/nanotube FETs are significantly less sensitive to many process parameter variations due to their inherent device structures and geometric properties. It is observed that a two-input NAND gate with nanowire or nanotube FETs shows a more than four times less performance variation than its bulk MOSFET counterpart and about two times less than FinFET devices at the 45 and 32 nm technologies, respectively. In other words, nanowire/nanotube FETs will have a larger margin for process parameter variations than bulk and FinFET devices for an allowable performance variation limit. While it is evident that process variations are going to be a major limiting factor for conventional MOSFET devices in future generations, this analysis is expected to further encourage nanowire and nanotube research for high-performance circuit applications.
引用
收藏
页码:2369 / 2376
页数:8
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