Impact of tilt angle variation on device performance

The control of tilt/twist angles during ion implantation process is becoming one the most challenging issue for future CMOS technologies. The continuous shrink of CMOS device dimensions imposes an accurate dopant placement within the transistor architecture. Moreover, improvement in the packing density increases the shadowing impact of resist patterns, leading to the use of quasi-vertical implants. In this paper, we propose to experimentally determine the sensitivity of standard electrical parameters of advanced technologies, sub-0.13-mum, to tilt angle variations that may occur within a wafer, within a lot, or lot to lot. Critical implants such as the high tilt implants (pockets) are studied for pMOS and nMOS transistors. Nominal results, obtained with the nominal tilt angle, are compared to the electrical results (threshold voltage, LAW, Short Channel Effects...) obtained for a modified tilt angle (+/-3degrees). Curves of sensitivity are then extracted. As a conclusion, specifications for the angle accuracy are proposed in order to insure a perfect matching of the device performance whatever the tilt angle discrepancies are.