Analyzing the impact of process variations on DRAM testing using border resistance traces

被引：0
|
作者：
Al-Ars, Z [1 ]
de Goor, AJV [1 ]
机构：
[1] Delft Univ Technol, Sect Comp Engn, Fac Informat Technol & Syst, NL-2628 CD Delft, Netherlands
来源：
ATS 2003: 12TH ASIAN TEST SYMPOSIUM, PROCEEDINGS | 2003年
关键词：
DRAMs; process variations; border resistance trace; defect simulation; memory testing;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
As a result of variations in the fabrication process, different memory components are produced with different operational characteristics, a situation that complicates the fault analysis process of manufactured memories. This paper discusses the issue of process variations, and shows how to deal with it in the context of fault analysis and test generation. The paper also introduces the concept of border resistance traces as a tool to optimize test stresses and inspect the impact of process variations on the optimization procedure. The concepts are discussed in the paper with the help of a practical example of a specific defect in the memory.
引用
收藏
页码：24 / 27
页数：4
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